Umamageswaran, Kothanda <br/><br/>
Formal semantics and proof techniques for optimizing VHDL models 

 - Boston  Kluwer Academic Publishers  1999 
 - 158 
<br/><br/><label>ISBN: </label>792383753 
<br/><br/><label>Subjects--Topical Terms: </label><br/>VHDL
<br/><br/><label>Dewey Class. No.: </label>621.392 UMA/F